Searched refs:CLK_TOP_APLL2_DIV5 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 137 #define CLK_TOP_APLL2_DIV5 126 macro
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| H A D | mt8173-clk.h | 142 #define CLK_TOP_APLL2_DIV5 132 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 523 DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
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| H A D | clk-mt8173-topckgen.c | 618 DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
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