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Searched refs:CLK_TOP_APLL2_DIV0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h132 #define CLK_TOP_APLL2_DIV0 121 macro
H A Dmt8173-clk.h137 #define CLK_TOP_APLL2_DIV0 127 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c518 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
H A Dclk-mt8173-topckgen.c613 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi861 <&topckgen CLK_TOP_APLL2_DIV0>,