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Searched refs:CLK_SRC_DISP1_0_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h693 #define CLK_SRC_DISP1_0_VAL 0x6 macro
878 #define CLK_SRC_DISP1_0_VAL 0x10666600 macro
H A Dclock_init_exynos5.c773 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); in exynos5250_system_clock_init()
932 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10); in exynos5420_system_clock_init()