Searched refs:CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK (Results 1 – 1 of 1) sorted by relevance
23 #define CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK GENMASK(7, 0) macro61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()82 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_set_parent()111 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_set_rate()148 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_set_rate_and_parent()