Searched refs:CLK_SCLK_MPLL (Results 1 – 5 of 5) sorted by relevance
/openbmc/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos4210-trats.dts | 220 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 228 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 236 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 244 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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H A D | exynos4210-universal_c210.dts | 234 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 242 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 250 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 258 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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H A D | exynos4210-i9100.dts | 319 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 328 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 336 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 345 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | exynos4.h | 21 #define CLK_SCLK_MPLL 9 macro
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/openbmc/linux/drivers/clk/samsung/ |
H A D | clk-exynos4.c | 467 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 544 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 1254 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL, 1384 clk_hw_get_rate(hws[CLK_SCLK_MPLL]), in exynos4_clk_init()
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