Searched refs:CLK_SCLK_CSIS0 (Results 1 – 5 of 5) sorted by relevance
160 <&clock CLK_SCLK_CSIS0>;163 <&clock CLK_SCLK_CSIS0>;
47 #define CLK_SCLK_CSIS0 134 macro
765 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
270 <&clock CLK_SCLK_CSIS0>;
458 <&clock CLK_SCLK_CSIS0>;