Searched refs:CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (Results 1 – 1 of 1) sorted by relevance
209 #define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) macro391 value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; in pcie_phy_enable()