Searched refs:CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (Results 1 – 1 of 1) sorted by relevance
213 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) macro370 value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; in pcie_phy_enable()