Searched refs:CLK_ROOT_PRE_DIV1 (Results 1 – 5 of 5) sorted by relevance
87 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in enable_usboh3_clk()562 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_esdhc()567 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_esdhc()572 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_esdhc()597 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_uart()602 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_uart()607 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_uart()612 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_uart()617 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_uart()622 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in init_clk_uart()[all …]
475 if (pre_div != CLK_ROOT_PRE_DIV1) { in clock_set_prediv()690 if (pre_div != CLK_ROOT_PRE_DIV1) { in clock_root_cfg()
13 CLK_ROOT_PRE_DIV1 = 0, enumerator
500 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in set_clk_enet()505 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in set_clk_enet()511 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | in set_clk_enet()529 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
330 CLK_ROOT_PRE_DIV1 = 0, enumerator