Searched refs:CLK_RESET_PLLX_BASE (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/arm/mach-tegra/ |
| H A D | sleep-tegra30.S | 56 #define CLK_RESET_PLLX_BASE 0xe0 macro
398 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
428 pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
697 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
722 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
724 str r0, [r5, #CLK_RESET_PLLX_BASE]
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra30.c | 124 #define CLK_RESET_PLLX_BASE 0xe0 macro
1130 readl(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_suspend()
1155 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()
1163 clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()
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