Searched refs:CLK_PCLK_DDR_PHY0 (Results 1 – 2 of 2) sorted by relevance
372 #define CLK_PCLK_DDR_PHY0 179 macro
1491 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",