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Searched refs:CLK_PCIEPHY0_REF (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml132 clocks = <&pmucru CLK_PCIEPHY0_REF>,
136 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi219 clocks = <&pmucru CLK_PCIEPHY0_REF>,
223 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
/openbmc/linux/include/dt-bindings/clock/
H A Drk3568-cru.h44 #define CLK_PCIEPHY0_REF 31 macro
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3568.c1551 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,