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Searched refs:CLK_MSDC_TOP_P_CFG (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8192-msdc.c32 GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg", "axi_sel", 7),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8192-clk.h402 #define CLK_MSDC_TOP_P_CFG 7 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi1347 <&msdc_top CLK_MSDC_TOP_P_CFG>,
1363 <&msdc_top CLK_MSDC_TOP_P_CFG>,