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Searched refs:CLK_MM_MDP_WROT0 (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c31 GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
H A Dclk-mt6795-mm.c45 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
H A Dclk-mt6797-mm.c45 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
H A Dclk-mt8183-mm.c53 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
H A Dclk-mt6779-mm.c53 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
H A Dclk-mt8173-mm.c48 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
H A Dclk-mt2712-mm.c56 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h227 #define CLK_MM_MDP_WROT0 13 macro
H A Dmediatek,mt6795-clk.h231 #define CLK_MM_MDP_WROT0 12 macro
H A Dmt6765-clk.h256 #define CLK_MM_MDP_WROT0 5 macro
H A Dmt8173-clk.h259 #define CLK_MM_MDP_WROT0 12 macro
H A Dmt2712-clk.h313 #define CLK_MM_MDP_WROT0 12 macro
H A Dmt6779-clk.h358 #define CLK_MM_MDP_WROT0 18 macro
H A Dmt8183-clk.h326 #define CLK_MM_MDP_WROT0 17 macro
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,mdp3-wrot.yaml82 clocks = <&mmsys CLK_MM_MDP_WROT0>;
H A Dmediatek-mdp.txt84 clocks = <&mmsys CLK_MM_MDP_WROT0>;
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1052 clocks = <&mmsys CLK_MM_MDP_WROT0>;
H A Dmt8183.dtsi1704 clocks = <&mmsys CLK_MM_MDP_WROT0>;