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Searched refs:CLK_MM_MDP_RSZ2 (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-mm.c40 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
H A Dclk-mt6797-mm.c41 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
H A Dclk-mt8173-mm.c44 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
H A Dclk-mt2712-mm.c51 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h223 #define CLK_MM_MDP_RSZ2 9 macro
H A Dmediatek,mt6795-clk.h226 #define CLK_MM_MDP_RSZ2 7 macro
H A Dmt8173-clk.h255 #define CLK_MM_MDP_RSZ2 8 macro
H A Dmt2712-clk.h308 #define CLK_MM_MDP_RSZ2 7 macro
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dmediatek-mdp.txt69 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1037 clocks = <&mmsys CLK_MM_MDP_RSZ2>;