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Searched refs:CLK_MM_DSI0_ENGINE (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-mm.c71 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
H A Dclk-mt8173-mm.c73 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
H A Dclk-mt2712-mm.c79 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h255 #define CLK_MM_DSI0_ENGINE 36 macro
H A Dmt8173-clk.h283 #define CLK_MM_DSI0_ENGINE 36 macro
H A Dmt2712-clk.h335 #define CLK_MM_DSI0_ENGINE 34 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1206 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,