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Searched refs:CLK_MM_DISP_UFBC_WDMA0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8192-mm.c49 GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8192-clk.h430 #define CLK_MM_DISP_UFBC_WDMA0 6 macro