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Searched refs:CLK_MM_DISP_SPLIT1 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-mm.c62 GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
H A Dclk-mt8173-mm.c65 GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h248 #define CLK_MM_DISP_SPLIT1 29 macro
H A Dmt8173-clk.h276 #define CLK_MM_DISP_SPLIT1 29 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1189 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;