Home
last modified time | relevance | path

Searched refs:CLK_MM_DISP_PWM0MM (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-mm.c67 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
H A Dclk-mt8173-mm.c69 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dmediatek,pwm-disp.yaml76 <&mmsys CLK_MM_DISP_PWM0MM>;
/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h251 #define CLK_MM_DISP_PWM0MM 32 macro
H A Dmt8173-clk.h279 #define CLK_MM_DISP_PWM0MM 32 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1254 <&mmsys CLK_MM_DISP_PWM0MM>;