Searched refs:CLK_HCLK_ARM_PLL_DIV_2 (Results 1 – 2 of 2) sorted by relevance
124 case CLK_HCLK_ARM_PLL_DIV_2: in get_sdram_clk_rate()
81 #define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) macro