Searched refs:CLK_GATE_PARENT (Results 1 – 1 of 1) sorted by relevance
149 #define CLK_GATE_PARENT(gname, cname, pname) \ macro175 CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),182 CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),