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Searched refs:CLK_GATE_OPEN (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock.c58 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); in clock_twi_onoff()
65 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); in clock_twi_onoff()
H A Dclock_sun9i.c76 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT + in clock_init_uart()
185 CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); in clock_twi_onoff()
192 CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); in clock_twi_onoff()
H A Dclock_sun4i.c61 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1)); in clock_init_uart()
72 CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); in clock_twi_onoff()
75 CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); in clock_twi_onoff()
H A Dclock_sun8i_a83t.c64 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + in clock_init_uart()
H A Dclock_sun6i.c96 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + in clock_init_uart()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock.h13 #define CLK_GATE_OPEN 0x1 macro
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dsunxi_nand_spl.c541 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); in nand_deselect()
/openbmc/u-boot/board/sunxi/
H A Dboard.c355 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); in nand_clock_setup()