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Searched refs:CLK_DIV_PERIL0_VAL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c72 writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); in system_clock_init()
H A Dexynos4_setup.h254 #define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ macro
/openbmc/u-boot/board/samsung/trats/
H A Dtrats.c332 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); in board_clock_init()
H A Dsetup.h209 #define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \ macro