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Searched refs:CLK_DIV_PERIC1_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h673 #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \ macro
851 #define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \ macro
H A Dclock_init_exynos5.c762 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); in exynos5250_system_clock_init()
953 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); in exynos5420_system_clock_init()