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Searched refs:CLK_DIV_PERIC0_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h664 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ macro
841 #define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \ macro
H A Dclock_init_exynos5.c759 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); in exynos5250_system_clock_init()
952 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); in exynos5420_system_clock_init()