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Searched refs:CLK_DIV_MPLL_PRE (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250-artik5-eval.dts51 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
H A Dexynos3250.dtsi485 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
/openbmc/linux/include/dt-bindings/clock/
H A Dexynos3250.h87 #define CLK_DIV_MPLL_PRE 68 macro
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c349 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),