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Searched refs:CLK_DIV_ISP2_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h210 #define CLK_DIV_ISP2_VAL 0x1 macro
H A Dclock_init_exynos5.c770 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); in exynos5250_system_clock_init()