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Searched refs:CLK_DIV_FSYS1_VAL (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c69 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in system_clock_init()
H A Dexynos5_setup.h489 #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE macro
757 #define CLK_DIV_FSYS1_VAL 0x04f13c4f macro
H A Dexynos4_setup.h204 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ macro
H A Dclock_init_exynos5.c942 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in exynos5420_system_clock_init()
/openbmc/u-boot/board/samsung/trats/
H A Dtrats.c329 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); in board_clock_init()
H A Dsetup.h156 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ macro