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Searched refs:CLK_DIV_CORE2 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dexynos4.h240 #define CLK_DIV_CORE2 461 macro
H A Dexynos3250.h121 #define CLK_DIV_CORE2 102 macro
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos4.c139 #define CLKS_NR (CLK_DIV_CORE2 + 1)
610 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
1387 clk_hw_get_rate(hws[CLK_DIV_CORE2])); in exynos4_clk_init()
H A Dclk-exynos3250.c422 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),