Home
last modified time | relevance | path

Searched refs:CLK_CTRL_DIV0_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_zynqmp.c95 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) macro
382 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_cpu_rate()
405 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_ddr_rate()
430 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_peripheral_rate()
465 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_wdt_rate()
476 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_wdt_rate()
542 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynqmp_clk_set_peripheral_rate()
H A Dclk_zynq.c33 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) macro
176 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_cpu_rate()
231 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_dci_rate()
248 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_peripheral_rate()
327 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynq_clk_set_peripheral_rate()