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Searched refs:CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h366 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L macro
H A Dbif_4_1_sh_mask.h237 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 macro
H A Dbif_5_0_sh_mask.h275 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 macro
H A Dbif_5_1_sh_mask.h239 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h20355 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK … macro
H A Dnbio_4_3_0_sh_mask.h17348 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK … macro
H A Dnbio_2_3_sh_mask.h1585 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK … macro
H A Dnbio_7_0_sh_mask.h117780 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK … macro
H A Dnbio_6_1_sh_mask.h17504 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK … macro