Home
last modified time | relevance | path

Searched refs:CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_pll_config.c105 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
H A Dclock_manager_gen5.c397 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; in cm_get_sdram_clk_hz()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h301 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 macro