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Searched refs:CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c218 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, in cm_basic_init()
396 reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> in cm_get_sdram_clk_hz()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h302 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff macro