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Searched refs:CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_pll_config.c109 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h306 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 macro