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Searched refs:CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_arria10.h130 #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1) macro
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c725 CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); in cm_full_cfg()