1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2016-2017 Intel Corporation 4 */ 5 6 #ifndef CLOCK_MANAGER_ARRIA10 7 #define CLOCK_MANAGER_ARRIA10 8 9 #ifndef __ASSEMBLER__ 10 11 struct socfpga_clock_manager_main_pll { 12 u32 vco0; 13 u32 vco1; 14 u32 en; 15 u32 ens; 16 u32 enr; 17 u32 bypass; 18 u32 bypasss; 19 u32 bypassr; 20 u32 mpuclk; 21 u32 nocclk; 22 u32 cntr2clk; 23 u32 cntr3clk; 24 u32 cntr4clk; 25 u32 cntr5clk; 26 u32 cntr6clk; 27 u32 cntr7clk; 28 u32 cntr8clk; 29 u32 cntr9clk; 30 u32 pad_0x48_0x5b[5]; 31 u32 cntr15clk; 32 u32 outrst; 33 u32 outrststat; 34 u32 nocdiv; 35 u32 pad_0x6c_0x80[5]; 36 }; 37 38 struct socfpga_clock_manager_per_pll { 39 u32 vco0; 40 u32 vco1; 41 u32 en; 42 u32 ens; 43 u32 enr; 44 u32 bypass; 45 u32 bypasss; 46 u32 bypassr; 47 u32 pad_0x20_0x27[2]; 48 u32 cntr2clk; 49 u32 cntr3clk; 50 u32 cntr4clk; 51 u32 cntr5clk; 52 u32 cntr6clk; 53 u32 cntr7clk; 54 u32 cntr8clk; 55 u32 cntr9clk; 56 u32 pad_0x48_0x5f[6]; 57 u32 outrst; 58 u32 outrststat; 59 u32 emacctl; 60 u32 gpiodiv; 61 u32 pad_0x70_0x80[4]; 62 }; 63 64 struct socfpga_clock_manager_altera { 65 u32 mpuclk; 66 u32 nocclk; 67 u32 mainmisc0; 68 u32 mainmisc1; 69 u32 perimisc0; 70 u32 perimisc1; 71 }; 72 73 struct socfpga_clock_manager { 74 /* clkmgr */ 75 u32 ctrl; 76 u32 intr; 77 u32 intrs; 78 u32 intrr; 79 u32 intren; 80 u32 intrens; 81 u32 intrenr; 82 u32 stat; 83 u32 testioctrl; 84 u32 _pad_0x24_0x40[7]; 85 /* mainpllgrp */ 86 struct socfpga_clock_manager_main_pll main_pll; 87 /* perpllgrp */ 88 struct socfpga_clock_manager_per_pll per_pll; 89 struct socfpga_clock_manager_altera altera; 90 }; 91 92 #ifdef CONFIG_SPL_BUILD 93 int cm_basic_init(const void *blob); 94 #endif 95 96 unsigned int cm_get_l4_sp_clk_hz(void); 97 unsigned long cm_get_mpu_clk_hz(void); 98 99 unsigned int cm_get_qspi_controller_clk_hz(void); 100 101 #endif /* __ASSEMBLER__ */ 102 103 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140 104 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144 105 #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ 106 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK) 107 108 /* value */ 109 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f 110 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff 111 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053 112 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001 113 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053 114 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001 115 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0 116 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1 117 #define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2 118 #define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0 119 #define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1 120 #define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2 121 #define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3 122 123 /* mask */ 124 #define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6) 125 #define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7) 126 #define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8) 127 #define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9) 128 #define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17) 129 #define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0) 130 #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1) 131 #define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2) 132 #define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3) 133 #define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4) 134 #define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0) 135 #define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1) 136 #define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2) 137 #define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3) 138 #define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4) 139 #define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0) 140 #define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1) 141 #define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2) 142 #define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3) 143 #define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8) 144 #define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9) 145 #define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10) 146 #define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11) 147 #define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0) 148 #define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300 149 #define CLKMGR_PERPLL_EN_RESET 0x00000f7f 150 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) 151 #define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003 152 #define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff 153 #define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f 154 #define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff 155 #define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003 156 #define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff 157 #define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f 158 #define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff 159 #define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007 160 #define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff 161 #define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0 162 #define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1 163 #define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2 164 #define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3 165 #define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4 166 #define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003 167 #define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff 168 #define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007 169 #define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0 170 #define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1 171 #define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2 172 #define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3 173 #define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4 174 175 #define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007 176 #define CLKMGR_PERPLLGRP_SRC_MAIN 0 177 #define CLKMGR_PERPLLGRP_SRC_PERI 1 178 #define CLKMGR_PERPLLGRP_SRC_OSC1 2 179 #define CLKMGR_PERPLLGRP_SRC_INTOSC 3 180 #define CLKMGR_PERPLLGRP_SRC_FPGA 4 181 182 /* bit shifting macro */ 183 #define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8 184 #define CLKMGR_PERPLL_VCO0_PSRC_LSB 8 185 #define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16 186 #define CLKMGR_PERPLL_VCO1_DENOM_LSB 16 187 #define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16 188 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 189 #define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0 190 #define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8 191 #define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16 192 #define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24 193 #define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26 194 #define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28 195 #define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16 196 #define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16 197 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 198 #define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16 199 #define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16 200 #define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16 201 #define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16 202 #define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16 203 #define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16 204 #define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16 205 #define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16 206 #define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26 207 #define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27 208 #define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28 209 210 /* PLL ramping work around */ 211 #define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000 212 #define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000 213 #define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000 214 #define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000 215 216 #define CLKMGR_STAT_BUSY BIT(0) 217 218 #endif /* CLOCK_MANAGER_ARRIA10 */ 219