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Searched refs:CLKMGR_L4_SP_CLK_SRC_MAINPLL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h220 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 macro
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c412 if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { in cm_get_l4_sp_clk_hz()