1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29 #include "dcn32/dcn32_clk_mgr_smu_msg.h"
30 #include "dcn20/dcn20_clk_mgr.h"
31 #include "dce100/dce_clk_mgr.h"
32 #include "dcn31/dcn31_clk_mgr.h"
33 #include "reg_helper.h"
34 #include "core_types.h"
35 #include "dm_helpers.h"
36 #include "link.h"
37
38 #include "atomfirmware.h"
39 #include "smu13_driver_if.h"
40
41 #include "dcn/dcn_3_2_0_offset.h"
42 #include "dcn/dcn_3_2_0_sh_mask.h"
43
44 #include "dcn32/dcn32_clk_mgr.h"
45 #include "dml/dcn32/dcn32_fpu.h"
46
47 #define DCN_BASE__INST0_SEG1 0x000000C0
48
49 #define mmCLK1_CLK_PLL_REQ 0x16E37
50 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
51 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
52 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
53 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
54 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
55
56 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
57 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
58 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
59 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
60 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
61 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
62
63 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
64 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64
65 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67
66 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A
67 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D
68 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70
69
70 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL
71 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L
72 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L
73 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
74 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
75 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
76
77 #undef FN
78 #define FN(reg_name, field_name) \
79 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
80
81 #define REG(reg) \
82 (clk_mgr->regs->reg)
83
84 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
85
86 #define BASE(seg) BASE_INNER(seg)
87
88 #define SR(reg_name)\
89 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
90 reg ## reg_name
91
92 #define CLK_SR_DCN32(reg_name)\
93 .reg_name = mm ## reg_name
94
95 static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
96 CLK_REG_LIST_DCN32()
97 };
98
99 static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
100 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
101 };
102
103 static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
104 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
105 };
106
107
108 #define CLK_SR_DCN321(reg_name, block, inst)\
109 .reg_name = mm ## block ## _ ## reg_name
110
111 static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
112 CLK_REG_LIST_DCN321()
113 };
114
115 static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
116 CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
117 };
118
119 static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
120 CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
121 };
122
123
124 /* Query SMU for all clock states for a particular clock */
dcn32_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)125 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
126 unsigned int *num_levels)
127 {
128 unsigned int i;
129 char *entry_i = (char *)entry_0;
130
131 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
132
133 if (ret & (1 << 31))
134 /* fine-grained, only min and max */
135 *num_levels = 2;
136 else
137 /* discrete, a number of fixed states */
138 /* will set num_levels to 0 on failure */
139 *num_levels = ret & 0xFF;
140
141 /* if the initial message failed, num_levels will be 0 */
142 for (i = 0; i < *num_levels; i++) {
143 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
145 }
146 }
147
dcn32_build_wm_range_table(struct clk_mgr_internal * clk_mgr)148 static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
149 {
150 DC_FP_START();
151 dcn32_build_wm_range_table_fpu(clk_mgr);
152 DC_FP_END();
153 }
154
dcn32_init_clocks(struct clk_mgr * clk_mgr_base)155 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
156 {
157 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
158 unsigned int num_levels;
159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
160 unsigned int i;
161
162 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
163 clk_mgr_base->clks.p_state_change_support = true;
164 clk_mgr_base->clks.prev_p_state_change_support = true;
165 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
166 clk_mgr->smu_present = false;
167 clk_mgr->dpm_present = false;
168
169 if (!clk_mgr_base->bw_params)
170 return;
171
172 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
173 clk_mgr->smu_present = true;
174
175 if (!clk_mgr->smu_present)
176 return;
177
178 dcn30_smu_check_driver_if_version(clk_mgr);
179 dcn30_smu_check_msg_header_version(clk_mgr);
180
181 /* DCFCLK */
182 dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
184 &num_entries_per_clk->num_dcfclk_levels);
185 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
186
187 /* SOCCLK */
188 dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
189 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
190 &num_entries_per_clk->num_socclk_levels);
191 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
192
193 /* DTBCLK */
194 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
195 dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
196 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
197 &num_entries_per_clk->num_dtbclk_levels);
198 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
199 dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
200 }
201
202 /* DISPCLK */
203 dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
204 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
205 &num_entries_per_clk->num_dispclk_levels);
206 num_levels = num_entries_per_clk->num_dispclk_levels;
207 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
208 //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
209 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
210 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
211
212 if (num_entries_per_clk->num_dcfclk_levels &&
213 num_entries_per_clk->num_dtbclk_levels &&
214 num_entries_per_clk->num_dispclk_levels)
215 clk_mgr->dpm_present = true;
216
217 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
218 for (i = 0; i < num_levels; i++)
219 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
220 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
221 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
222 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
223 }
224 for (i = 0; i < num_levels; i++)
225 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
226 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
227
228 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
229 for (i = 0; i < num_levels; i++)
230 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
231 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
232 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
233 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
234 }
235
236 /* Get UCLK, update bounding box */
237 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
238
239 DC_FP_START();
240 /* WM range table */
241 dcn32_build_wm_range_table(clk_mgr);
242 DC_FP_END();
243 }
244
dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)245 static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
246 struct dc_state *context,
247 int ref_dtbclk_khz)
248 {
249 struct dccg *dccg = clk_mgr->dccg;
250 uint32_t tg_mask = 0;
251 int i;
252
253 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
254 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
255 struct dtbclk_dto_params dto_params = {0};
256
257 /* use mask to program DTO once per tg */
258 if (pipe_ctx->stream_res.tg &&
259 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
260 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
261
262 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
263 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
264
265 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
266 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
267 }
268 }
269 }
270
271 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
272 * update DPPCLK to be the exact frequency that will be set after the DPPCLK
273 * divider is updated. This will prevent rounding issues that could cause DPP
274 * refclk and DPP DTO to not match up.
275 */
dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal * clk_mgr,struct dc_clocks * new_clocks)276 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
277 {
278 int dpp_divider = 0;
279 int disp_divider = 0;
280
281 if (new_clocks->dppclk_khz) {
282 dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
283 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
284 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
285 }
286 if (new_clocks->dispclk_khz > 0) {
287 disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
288 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
289 new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
290 }
291 }
292
dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)293 void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
294 struct dc_state *context, bool safe_to_lower)
295 {
296 int i;
297
298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
299 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
300 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
301
302 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
303
304 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
305 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
306 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
307 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
308 * In this case just continue in loop
309 */
310 continue;
311 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
312 /* The software state is not valid if dpp resource is NULL and
313 * dppclk_khz > 0.
314 */
315 ASSERT(false);
316 continue;
317 }
318
319 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
320
321 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
322 clk_mgr->dccg->funcs->update_dpp_dto(
323 clk_mgr->dccg, dpp_inst, dppclk_khz);
324 }
325 }
326
dcn32_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)327 static void dcn32_update_clocks_update_dentist(
328 struct clk_mgr_internal *clk_mgr,
329 struct dc_state *context)
330 {
331 uint32_t new_disp_divider = 0;
332 uint32_t new_dispclk_wdivider = 0;
333 uint32_t old_dispclk_wdivider = 0;
334 uint32_t i;
335 uint32_t dentist_dispclk_wdivider_readback = 0;
336 struct dc *dc = clk_mgr->base.ctx->dc;
337
338 if (clk_mgr->base.clks.dispclk_khz == 0)
339 return;
340
341 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
342 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
343
344 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
345 REG_GET(DENTIST_DISPCLK_CNTL,
346 DENTIST_DISPCLK_WDIVIDER, &old_dispclk_wdivider);
347
348 /* When changing divider to or from 127, some extra programming is required to prevent corruption */
349 if (old_dispclk_wdivider == 127 && new_dispclk_wdivider != 127) {
350 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
351 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
352 uint32_t fifo_level;
353 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
354 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
355 int32_t N;
356 int32_t j;
357
358 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
359 continue;
360 /* Virtual encoders don't have this function */
361 if (!stream_enc->funcs->get_fifo_cal_average_level)
362 continue;
363 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
364 stream_enc);
365 N = fifo_level / 4;
366 dccg->funcs->set_fifo_errdet_ovr_en(
367 dccg,
368 true);
369 for (j = 0; j < N - 4; j++)
370 dccg->funcs->otg_drop_pixel(
371 dccg,
372 pipe_ctx->stream_res.tg->inst);
373 dccg->funcs->set_fifo_errdet_ovr_en(
374 dccg,
375 false);
376 }
377 } else if (new_dispclk_wdivider == 127 && old_dispclk_wdivider != 127) {
378 /* request clock with 126 divider first */
379 uint32_t temp_disp_divider = dentist_get_divider_from_did(126);
380 uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;
381
382 if (clk_mgr->smu_present)
383 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(temp_dispclk_khz));
384
385 if (dc->debug.override_dispclk_programming) {
386 REG_GET(DENTIST_DISPCLK_CNTL,
387 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
388
389 if (dentist_dispclk_wdivider_readback != 126) {
390 REG_UPDATE(DENTIST_DISPCLK_CNTL,
391 DENTIST_DISPCLK_WDIVIDER, 126);
392 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
393 }
394 }
395
396 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
397 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
398 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
399 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
400 uint32_t fifo_level;
401 int32_t N;
402 int32_t j;
403
404 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
405 continue;
406 /* Virtual encoders don't have this function */
407 if (!stream_enc->funcs->get_fifo_cal_average_level)
408 continue;
409 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
410 stream_enc);
411 N = fifo_level / 4;
412 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
413 for (j = 0; j < 12 - N; j++)
414 dccg->funcs->otg_add_pixel(dccg,
415 pipe_ctx->stream_res.tg->inst);
416 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
417 }
418 }
419
420 /* do requested DISPCLK updates*/
421 if (clk_mgr->smu_present)
422 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_khz));
423
424 if (dc->debug.override_dispclk_programming) {
425 REG_GET(DENTIST_DISPCLK_CNTL,
426 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
427
428 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
429 REG_UPDATE(DENTIST_DISPCLK_CNTL,
430 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
431 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
432 }
433 }
434
435 }
436
dcn32_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base)437 static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
438 {
439 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
440 uint32_t dispclk_wdivider;
441 int disp_divider;
442
443 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
444 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
445
446 /* Return DISPCLK freq in Khz */
447 if (disp_divider)
448 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
449
450 return 0;
451 }
452
453
dcn32_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)454 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
455 struct dc_state *context,
456 bool safe_to_lower)
457 {
458 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
459 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
460 struct dc *dc = clk_mgr_base->ctx->dc;
461 int display_count;
462 bool update_dppclk = false;
463 bool update_dispclk = false;
464 bool enter_display_off = false;
465 bool dpp_clock_lowered = false;
466 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
467 bool force_reset = false;
468 bool update_uclk = false, update_fclk = false;
469 bool p_state_change_support;
470 bool fclk_p_state_change_support;
471
472 if (clk_mgr_base->clks.dispclk_khz == 0 ||
473 (dc->debug.force_clock_mode & 0x1)) {
474 /* This is from resume or boot up, if forced_clock cfg option used,
475 * we bypass program dispclk and DPPCLK, but need set them for S3.
476 */
477 force_reset = true;
478
479 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
480
481 /* Force_clock_mode 0x1: force reset the clock even it is the same clock
482 * as long as it is in Passive level.
483 */
484 }
485 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
486
487 if (display_count == 0)
488 enter_display_off = true;
489
490 if (clk_mgr->smu_present) {
491 if (enter_display_off == safe_to_lower)
492 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
493
494 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
495
496 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support;
497
498 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
499 !dc->work_arounds.clock_update_disable_mask.fclk) {
500 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
501
502 /* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */
503 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
504 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
505 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
506 }
507 }
508
509 if (dc->debug.force_min_dcfclk_mhz > 0)
510 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
511 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
512
513 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
514 !dc->work_arounds.clock_update_disable_mask.dcfclk) {
515 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
516 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
517 }
518
519 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
520 !dc->work_arounds.clock_update_disable_mask.dcfclk_ds) {
521 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
522 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
523 }
524
525 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
526 /* We don't actually care about socclk, don't notify SMU of hard min */
527 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
528
529 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
530 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
531
532 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
533 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
534 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
535 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
536 }
537
538 p_state_change_support = new_clocks->p_state_change_support;
539 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) &&
540 !dc->work_arounds.clock_update_disable_mask.uclk) {
541 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
542
543 /* to disable P-State switching, set UCLK min = max */
544 if (!clk_mgr_base->clks.p_state_change_support) {
545 if (dc->clk_mgr->dc_mode_softmax_enabled) {
546 /* On DCN32x we will never have the functional UCLK min above the softmax
547 * since we calculate mode support based on softmax being the max UCLK
548 * frequency.
549 */
550 if (dc->debug.disable_dc_mode_overwrite) {
551 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
552 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
553 } else
554 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
555 dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
556 } else {
557 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
558 }
559 }
560 }
561
562 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
563 dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, true);
564 else
565 dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, false);
566
567 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
568 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
569 update_fclk = true;
570 }
571
572 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk &&
573 !dc->work_arounds.clock_update_disable_mask.fclk) {
574 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
575 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
576 }
577
578 /* Always update saved value, even if new value not set due to P-State switching unsupported */
579 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz) &&
580 !dc->work_arounds.clock_update_disable_mask.uclk) {
581 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
582 update_uclk = true;
583 }
584
585 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
586 if (clk_mgr_base->clks.p_state_change_support &&
587 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
588 !dc->work_arounds.clock_update_disable_mask.uclk) {
589 if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)
590 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
591 max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
592
593 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
594 }
595
596 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
597 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
598 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
599 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
600 }
601 }
602
603 dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
604 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
605 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
606 dpp_clock_lowered = true;
607
608 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
609
610 if (clk_mgr->smu_present && !dpp_clock_lowered)
611 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
612
613 update_dppclk = true;
614 }
615
616 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
617 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
618
619 update_dispclk = true;
620 }
621
622 if (!new_clocks->dtbclk_en) {
623 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
624 }
625
626 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
627 if (!dc->debug.disable_dtb_ref_clk_switch &&
628 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
629 /* DCCG requires KHz precision for DTBCLK */
630 clk_mgr_base->clks.ref_dtbclk_khz =
631 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
632 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
633 }
634
635 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
636 if (dpp_clock_lowered) {
637 /* if clock is being lowered, increase DTO before lowering refclk */
638 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
639 dcn32_update_clocks_update_dentist(clk_mgr, context);
640 if (clk_mgr->smu_present)
641 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
642 } else {
643 /* if clock is being raised, increase refclk before lowering DTO */
644 if (update_dppclk || update_dispclk)
645 dcn32_update_clocks_update_dentist(clk_mgr, context);
646 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
647 * that we do not lower dto when it is not safe to lower. We do not need to
648 * compare the current and new dppclk before calling this function.
649 */
650 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
651 }
652 }
653
654 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
655 /*update dmcu for wait_loop count*/
656 dmcu->funcs->set_psr_wait_loop(dmcu,
657 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
658 }
659
dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)660 static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
661 {
662 struct fixed31_32 pll_req;
663 uint32_t pll_req_reg = 0;
664
665 /* get FbMult value */
666 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
667 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
668 else
669 pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
670
671 /* set up a fixed-point number
672 * this works because the int part is on the right edge of the register
673 * and the frac part is on the left edge
674 */
675 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
676 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
677
678 /* multiply by REFCLK period */
679 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
680
681 return dc_fixpt_floor(pll_req);
682 }
683
dcn32_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)684 static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
685 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
686 {
687 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
688 uint32_t dprefclk_did = 0;
689 uint32_t dcfclk_did = 0;
690 uint32_t dtbclk_did = 0;
691 uint32_t dispclk_did = 0;
692 uint32_t dppclk_did = 0;
693 uint32_t target_div = 0;
694
695 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
696 /* DFS Slice 0 is used for DISPCLK */
697 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
698 /* DFS Slice 1 is used for DPPCLK */
699 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
700 /* DFS Slice 2 is used for DPREFCLK */
701 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
702 /* DFS Slice 3 is used for DCFCLK */
703 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
704 /* DFS Slice 4 is used for DTBCLK */
705 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
706 } else {
707 /* DFS Slice 0 is used for DISPCLK */
708 dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
709 /* DFS Slice 1 is used for DPPCLK */
710 dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
711 /* DFS Slice 2 is used for DPREFCLK */
712 dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
713 /* DFS Slice 3 is used for DCFCLK */
714 dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
715 /* DFS Slice 4 is used for DTBCLK */
716 dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
717 }
718
719 /* Convert DISPCLK DFS Slice DID to divider*/
720 target_div = dentist_get_divider_from_did(dispclk_did);
721 //Get dispclk in khz
722 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
723 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
724
725 /* Convert DISPCLK DFS Slice DID to divider*/
726 target_div = dentist_get_divider_from_did(dppclk_did);
727 //Get dppclk in khz
728 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
729 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
730
731 /* Convert DPREFCLK DFS Slice DID to divider*/
732 target_div = dentist_get_divider_from_did(dprefclk_did);
733 //Get dprefclk in khz
734 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
735 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
736
737 /* Convert DCFCLK DFS Slice DID to divider*/
738 target_div = dentist_get_divider_from_did(dcfclk_did);
739 //Get dcfclk in khz
740 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
741 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
742
743 /* Convert DTBCLK DFS Slice DID to divider*/
744 target_div = dentist_get_divider_from_did(dtbclk_did);
745 //Get dtbclk in khz
746 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
747 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
748 }
749
dcn32_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)750 static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
751 {
752 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
753 int ss_info_num = bp->funcs->get_ss_entry_number(
754 bp, AS_SIGNAL_TYPE_GPU_PLL);
755
756 if (ss_info_num) {
757 struct spread_spectrum_info info = { { 0 } };
758 enum bp_result result = bp->funcs->get_spread_spectrum_info(
759 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
760
761 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
762 * that SS is enabled
763 */
764 if (result == BP_RESULT_OK &&
765 info.spread_spectrum_percentage != 0) {
766 clk_mgr->ss_on_dprefclk = true;
767 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
768
769 if (info.type.CENTER_MODE == 0) {
770 /* Currently for DP Reference clock we
771 * need only SS percentage for
772 * downspread
773 */
774 clk_mgr->dprefclk_ss_percentage =
775 info.spread_spectrum_percentage;
776 }
777 }
778 }
779 }
dcn32_notify_wm_ranges(struct clk_mgr * clk_mgr_base)780 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
781 {
782 unsigned int i;
783 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
784 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
785
786 if (!clk_mgr->smu_present)
787 return;
788
789 if (!table)
790 return;
791
792 memset(table, 0, sizeof(*table));
793
794 /* collect valid ranges, place in pmfw table */
795 for (i = 0; i < WM_SET_COUNT; i++)
796 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
797 table->Watermarks.WatermarkRow[i].WmSetting = i;
798 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
799 }
800 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
801 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
802 dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
803 }
804
805 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn32_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)806 static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
807 {
808 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
809
810 if (!clk_mgr->smu_present)
811 return;
812
813 if (current_mode) {
814 if (clk_mgr_base->clks.p_state_change_support)
815 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
816 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
817 else
818 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
819 clk_mgr_base->bw_params->max_memclk_mhz);
820 } else {
821 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
822 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
823 }
824 }
825
826 /* Set max memclk to highest DPM value */
dcn32_set_hard_max_memclk(struct clk_mgr * clk_mgr_base)827 static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
828 {
829 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
830
831 if (!clk_mgr->smu_present)
832 return;
833
834 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
835 }
836
837 /* Get current memclk states, update bounding box */
dcn32_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)838 static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
839 {
840 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
841 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
842 unsigned int num_levels;
843
844 if (!clk_mgr->smu_present)
845 return;
846
847 /* Refresh memclk and fclk states */
848 dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
849 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
850 &num_entries_per_clk->num_memclk_levels);
851 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
852 clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
853
854 /* memclk must have at least one level */
855 num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
856
857 dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
858 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
859 &num_entries_per_clk->num_fclk_levels);
860 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
861
862 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
863 num_levels = num_entries_per_clk->num_memclk_levels;
864 } else {
865 num_levels = num_entries_per_clk->num_fclk_levels;
866 }
867 clk_mgr_base->bw_params->max_memclk_mhz =
868 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
869 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
870
871 if (clk_mgr->dpm_present && !num_levels)
872 clk_mgr->dpm_present = false;
873
874 if (!clk_mgr->dpm_present)
875 dcn32_patch_dpm_table(clk_mgr_base->bw_params);
876
877 DC_FP_START();
878 /* Refresh bounding box */
879 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
880 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
881 DC_FP_END();
882 }
883
dcn32_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)884 static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
885 struct dc_clocks *b)
886 {
887 if (a->dispclk_khz != b->dispclk_khz)
888 return false;
889 else if (a->dppclk_khz != b->dppclk_khz)
890 return false;
891 else if (a->dcfclk_khz != b->dcfclk_khz)
892 return false;
893 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
894 return false;
895 else if (a->dramclk_khz != b->dramclk_khz)
896 return false;
897 else if (a->p_state_change_support != b->p_state_change_support)
898 return false;
899 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
900 return false;
901
902 return true;
903 }
904
dcn32_enable_pme_wa(struct clk_mgr * clk_mgr_base)905 static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
906 {
907 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
908
909 if (!clk_mgr->smu_present)
910 return;
911
912 dcn32_smu_set_pme_workaround(clk_mgr);
913 }
914
dcn32_is_smu_present(struct clk_mgr * clk_mgr_base)915 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
916 {
917 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
918 return clk_mgr->smu_present;
919 }
920
dcn32_set_max_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz)921 static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
922 {
923 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
924
925 if (!clk_mgr->smu_present)
926 return;
927
928 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
929 }
930
dcn32_set_min_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz)931 static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
932 {
933 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
934
935 if (!clk_mgr->smu_present)
936 return;
937
938 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
939 }
940
941 static struct clk_mgr_funcs dcn32_funcs = {
942 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
943 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
944 .update_clocks = dcn32_update_clocks,
945 .dump_clk_registers = dcn32_dump_clk_registers,
946 .init_clocks = dcn32_init_clocks,
947 .notify_wm_ranges = dcn32_notify_wm_ranges,
948 .set_hard_min_memclk = dcn32_set_hard_min_memclk,
949 .set_hard_max_memclk = dcn32_set_hard_max_memclk,
950 .set_max_memclk = dcn32_set_max_memclk,
951 .set_min_memclk = dcn32_set_min_memclk,
952 .get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
953 .are_clock_states_equal = dcn32_are_clock_states_equal,
954 .enable_pme_wa = dcn32_enable_pme_wa,
955 .is_smu_present = dcn32_is_smu_present,
956 .get_dispclk_from_dentist = dcn32_get_dispclk_from_dentist,
957 };
958
dcn32_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)959 void dcn32_clk_mgr_construct(
960 struct dc_context *ctx,
961 struct clk_mgr_internal *clk_mgr,
962 struct pp_smu_funcs *pp_smu,
963 struct dccg *dccg)
964 {
965 struct clk_log_info log_info = {0};
966
967 clk_mgr->base.ctx = ctx;
968 clk_mgr->base.funcs = &dcn32_funcs;
969 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
970 clk_mgr->regs = &clk_mgr_regs_dcn321;
971 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
972 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
973 } else {
974 clk_mgr->regs = &clk_mgr_regs_dcn32;
975 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
976 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
977 }
978
979 clk_mgr->dccg = dccg;
980 clk_mgr->dfs_bypass_disp_clk = 0;
981
982 clk_mgr->dprefclk_ss_percentage = 0;
983 clk_mgr->dprefclk_ss_divider = 1000;
984 clk_mgr->ss_on_dprefclk = false;
985 clk_mgr->dfs_ref_freq_khz = 100000;
986
987 /* Changed from DCN3.2_clock_frequency doc to match
988 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
989 * dprefclk DID divider
990 */
991 clk_mgr->base.dprefclk_khz = 716666;
992 if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
993 //initialize DTB ref clock value if DPM disabled
994 if (ctx->dce_version == DCN_VERSION_3_21)
995 clk_mgr->base.clks.ref_dtbclk_khz = 477800;
996 else
997 clk_mgr->base.clks.ref_dtbclk_khz = 268750;
998 }
999
1000
1001 /* integer part is now VCO frequency in kHz */
1002 clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
1003
1004 /* in case we don't get a value from the register, use default */
1005 if (clk_mgr->base.dentist_vco_freq_khz == 0)
1006 clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
1007
1008 dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1009
1010 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
1011 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
1012 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
1013 }
1014
1015 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
1016 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
1017 }
1018 dcn32_clock_read_ss_info(clk_mgr);
1019
1020 clk_mgr->dfs_bypass_enabled = false;
1021
1022 clk_mgr->smu_present = false;
1023
1024 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1025
1026 /* need physical address of table to give to PMFW */
1027 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
1028 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
1029 &clk_mgr->wm_range_table_addr);
1030 }
1031
dcn32_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)1032 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
1033 {
1034 kfree(clk_mgr->base.bw_params);
1035
1036 if (clk_mgr->wm_range_table)
1037 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
1038 clk_mgr->wm_range_table);
1039 }
1040
1041