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Searched refs:CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h177 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 macro
H A Dsmu_7_1_1_sh_mask.h171 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 macro
H A Dsmu_7_1_0_sh_mask.h171 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 macro
H A Dsmu_7_0_1_sh_mask.h171 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 macro
H A Dsmu_7_1_3_sh_mask.h197 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 macro
H A Dsmu_7_1_2_sh_mask.h171 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 macro