Home
last modified time | relevance | path

Searched refs:CG_SCLK_DPM_CTRL (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsumo_dpm.c480 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
483 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
486 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
489 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
586 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
589 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
592 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
595 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
H A Dsumod.h182 #define CG_SCLK_DPM_CTRL 0x684 macro