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Searched refs:CGTS_CU3_SP0_CTRL_REG__SP00_MASK (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h9621 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f macro
H A Dgfx_8_0_sh_mask.h11345 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f macro
H A Dgfx_8_1_sh_mask.h11743 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h24245 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK … macro
H A Dgc_9_2_1_sh_mask.h25667 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK … macro
H A Dgc_9_1_sh_mask.h25536 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK … macro
H A Dgc_9_4_3_sh_mask.h28052 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK … macro
H A Dgc_9_4_2_sh_mask.h17999 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK … macro