Searched refs:CCM_PLL5_CTRL_DDR_CLK (Results 1 – 2 of 2) sorted by relevance
241 #define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) macro
291 setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); in mctl_setup_dram_clock()