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Searched refs:CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c789 CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK | in enable_pll_video()
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h766 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u macro
768 …2_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK)