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Searched refs:CCI400_SRC_PLL_PERIPH0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c57 writel(CCI400_SRC_PLL_PERIPH0 | CCI400_CLK_DIV_RATIO(2), in clock_init_safe()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h175 #define CCI400_SRC_PLL_PERIPH0 (0x1 << CCI400_SRC_CLK_SELECT_SHIFT) macro