Home
last modified time | relevance | path

Searched refs:C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_3_sh_mask.h125417 #define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_sh_mask.h104460 #define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT … macro