Searched refs:C20_MPLLB_TX_CLK_DIV_MASK (Results 1 – 2 of 2) sorted by relevance
209 #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) macro233 #define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)
2382 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()