Searched refs:C20_FB_CLK_DIV4_EN (Results 1 – 2 of 2) sorted by relevance
205 #define C20_FB_CLK_DIV4_EN REG_BIT(13) macro
2394 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()