Searched refs:BOOL_TO_MASK (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/target/riscv/ |
| H A D | time_helper.c | 30 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); in riscv_vstimer_cb()
36 riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_stimer_cb()
74 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); in riscv_timer_write_timecmp()
76 riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1)); in riscv_timer_write_timecmp()
84 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); in riscv_timer_write_timecmp()
86 riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); in riscv_timer_write_timecmp()
154 riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); in riscv_timer_disable_timecmp()
164 riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); in riscv_timer_disable_timecmp()
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| H A D | pmu.c | 133 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in riscv_pmu_incr_ctr_rv32()
172 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in riscv_pmu_incr_ctr_rv64()
517 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); in pmu_timer_trigger_irq()
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