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Searched refs:BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h1757 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL macro
H A Ddce_8_0_sh_mask.h3247 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff macro
H A Ddce_10_0_sh_mask.h3169 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff macro
H A Ddce_11_0_sh_mask.h3239 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff macro
H A Ddce_11_2_sh_mask.h3487 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff macro
H A Ddce_12_0_sh_mask.h9322 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21321 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
H A Ddcn_2_1_0_sh_mask.h43307 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
H A Ddcn_3_2_1_sh_mask.h41940 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
H A Ddcn_1_0_sh_mask.h40073 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
H A Ddcn_3_0_2_sh_mask.h42591 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
H A Ddcn_3_0_0_sh_mask.h49187 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
H A Ddcn_2_0_0_sh_mask.h48816 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro
H A Ddcn_3_2_0_sh_mask.h41892 #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … macro