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Searched refs:BASEADDR_V7M_SCB (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/arch/arm/mm/
H A Dpmsa-v7.c105 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR); in rgnr_write()
113 u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(15, 0); in dracr_write()
115 writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR); in dracr_write()
121 u32 racr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(31, 16); in drsr_write()
123 writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR); in drsr_write()
129 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR); in drbar_write()
134 return readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RBAR); in drbar_read()
H A Dpmsa-v8.c53 return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR); in prlar_read()
58 return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR); in prbar_read()
63 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR); in prsel_write()
68 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR); in prbar_write()
73 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR); in prlar_write()
H A Dproc-v7m.S76 movw r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
77 movt r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
88 movw r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
89 movt r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
111 ldr r0, =BASEADDR_V7M_SCB
H A Dproc-macros.S76 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
77 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
94 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
95 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
H A Dcache-v7m.S25 movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
26 movt \rt, #:upper16:BASEADDR_V7M_SCB + \reg
31 movw\c \tmp, #:lower16:BASEADDR_V7M_SCB + \op
32 movt\c \tmp, #:upper16:BASEADDR_V7M_SCB + \op
/openbmc/linux/arch/arm/include/asm/
H A Dcputype.h159 return readl(BASEADDR_V7M_SCB + offset); in read_cpuid_ext()
203 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); in read_cpuid_id()
208 return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR); in read_cpuid_cachetype()
213 return readl(BASEADDR_V7M_SCB + MPU_TYPE); in read_cpuid_mputype()
H A Dcachetype.h90 writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR); in set_csselr()
95 return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); in read_ccsidr()
H A Dv7m.h8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) macro
/openbmc/linux/arch/arm/kernel/
H A Dv7m.c14 BASEADDR_V7M_SCB + V7M_SCB_AIRCR); in armv7m_restart()
H A Dhead-nommu.S60 ldr r9, =BASEADDR_V7M_SCB
133 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
134 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
256 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
257 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
H A Dentry-v7m.S64 ldr r1, =BASEADDR_V7M_SCB
/openbmc/linux/drivers/irqchip/
H A Dirq-nvic.c42 unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR); in nvic_handle_irq()
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S692 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
693 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR